The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-die microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. As the use of these devices has become more prevalent, the demand for faster operation and better reliability has increased.
An important part in the circuit design, construction, and manufacture of semiconductor devices concerns semiconductor memories; the circuitry used to store digital information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. SRAMs are mainly used in applications that require a high random access speed and/or a CMOS logic compatible process. DRAMs, on the other hand, are mainly used for high-density applications where the slow random access speed of DRAM can be tolerated.
Some SRAM cell designs are based on NDR (Negative Differential Resistance) devices. They usually consist of at least two active elements, including an NDR device. The NDR device is important to the overall performance of this type of SRAM cell. A variety of NDR devices have been introduced ranging from a simple bipolar transistor to complicated quantum-effect devices. One advantage of the NDR-based cell is the potential of having a cell area smaller than conventional SRAM cells (e.g., either 4T or 6T cells) because of the smaller number of active devices and interconnections. Many of the NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. Some of these problems include: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for the cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise margins; limitations in access speed due to slow switching from one state to the other, limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
A novel type of NDR-based SRAM (“thin capacitively-coupled thyristor RAM”) has been recently introduced that can potentially provide the speed of conventional SRAM at the density of DRAM in a CMOS compatible process. This new SRAM cell uses a thin capacitively-coupled NDR device and more specifically a thin capacitively-coupled thyristor to form a bistable element for the SRAM cell. For more details of specific examples of this new device, reference may be made to: “A Novel High Density, Low Voltage SRAM Cell With A Vertical NDR Device,” VLSI Technology Technical Digest, June, 1998; “A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-Scale Memories,” International Electron Device Meeting Technical Digest 1999, and “A Semiconductor Capacitively-Coupled NDR Device And Its Applications For High-Speed High-Density Memories And Power Switches,” PCT Int'l Publication No. WO 99/63598, corresponding to U.S. patent application Ser. No. 09/1092449, now U.S. Pat. No. 6,229,161 (Nemati, et al.). Each of these documents is incorporated by reference in its entirety.
An important design consideration in any type of thyristor-based memory cell. including a thin capacitively-coupled thyristor RAM cell, is the holding current of the thyristor. The holding current of the thyristor is the minimum current that keeps the thyristor in the forward conducting state. This holding current has to be sufficiently low so that the memory cell has an acceptable standby current. For example, a holding current larger than a few nano-Amperes per cell could significantly limit the maximum capacity of a thyristor-based memory.
Another important consideration when using a thyristor-based memory cell is the sensitivity of the blocking state of the thyristor to various adverse conditions such as noise, light, anode-to-cathode voltage changes and high temperatures. These sensitivities can affect the operation of the thyristor, resulting in undesirable turn-on, which disrupts the contents of the memory cell.